FEMTO: Fast error analysis in Multipliers through Topological Traversal

Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there are few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate multipliers, which are a key hardware component used in error-resilient applications, and presents a novel algorithm that efficiently determines the probability distribution of the error introduced by the approximation. The accuracy of the technique is demonstrated to be comparable to Monte Carlo simulations, while being significantly less computationally intensive.