Power-down circuit synthesis for analog/mixed-signal

Due to the need for energy efficiency, power management features of modern systems on chips are becoming more and more complex. The complexity also affects analog/mixed-signal circuit blocks. They are equipped with power-down modes to shut off bias currents while the block is not used. In industrial practice, the power-down circuitry is added manually towards the end of the design phase. Due to the increasing complexity of the power-down functionality, fault-free implementation and verification are becoming more and more challenging and time consuming. In this work, we are going one step beyond verification to an automatic, i.e., fault free synthesis of power-down circuitry. We formulate the power-down synthesis problem and solve it by combining a new rip-up algorithm with a constraint programming formulation. To the best of our knowledge, the first synthesis algorithm for power-down circuit synthesis for analog/mixed-signal blocks is presented. The ability to successfully synthesize the power-down circuitry is demonstrated for three amplifier circuits and a voltage-controlled oscillator.