DocumentCode :
3723738
Title :
A vertical super-junction strained-silicon channel power MOSFET
Author :
Mayank Punetha;Yashvir Singh;Shardul Thapliyal
Author_Institution :
Department of Electronics and Communication Engineeringm G. B. Pant Engineering College, Pauri Garhwal, Uttarakhand-246194, INDIA
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, we propose a vertical super-junction strained-Si channel power MOSFET to improve the breakdown voltage, drain current, threshold voltage, and transconductance. In the proposed structure, a P-pillar forming super-junction with N-drift region is incorporated to get higher blocking voltage due to reduction in electric field inside the drift region. In order to lower the on-resistance, the proposed device uses a strained-Si channel which is created with the help of a relaxed Si0.8Ge0.2 layer over a compositionally graded Si1-xGex buffer. This also increases the current drivability, reduces the threshold voltage and enhances the transconductance. Based on 2D simulations, the proposed MOSFET is shown to achieve 37% improvement in breakdown voltage, 44% increase in driving current, 60% reduction in threshold voltage, and 22% improvement in peak transconductance as compared to the conventional power MOSFET.
Keywords :
"MOSFET","Silicon","Threshold voltage","Electric fields","Strain","Semiconductor process modeling","Transconductance"
Publisher :
ieee
Conference_Titel :
TENCON 2015 - 2015 IEEE Region 10 Conference
ISSN :
2159-3442
Print_ISBN :
978-1-4799-8639-2
Electronic_ISBN :
2159-3450
Type :
conf
DOI :
10.1109/TENCON.2015.7372981
Filename :
7372981
Link To Document :
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