A low-resource low-latency hybrid adaptive CORDIC in 180-nm CMOS technology

In this paper, a low-resource low-latency hybrid adaptive COordinate Rotation DIgital Computer (HA-CORDIC) is implemented both in FPGA and 180-nm CMOS technology. The adaptive algorithm reduces around 50% iterations in comparison with the conventional CORDIC algorithm. The hybrid architecture together with resource sharing, parallel and pipeline processing are utilized in HA-CORDIC implementation. In FPGA implementation, the results show that the proposed system can operate at 108.15-MHz frequency, with 716 LUTs and 473 registers resource consumption. In CMOS implementation, the hardware architecture costs 10,299 cells with 0.41 mm2 area and fully operates at 50-MHz frequency.