Voltage droop aware task mapping for multi-core systems with on-chip voltage regulator

Reliable power supply is essential for the robust operations of the chip. Due to the physical properties of the silicon and the transient workload, the supply voltage will drop significantly, even under the nominal operating level. Severe voltage droop in the on-chip power delivery network results in long signal propagation delay and even catastrophic failures. In order to alleviate the problem, the relationship between the workload and the voltage droop is first investigated on an on-chip power grid, which is a fine-grained and regular mesh to power up the components. In this paper, we have proposed a novel voltage droop-aware task mapping approach to minimize the overall voltage droop at runtime. A simulation platform based on SPICE and C++ is developed to evaluate the proposed task mapping algorithm. Experimental results show that the proposed algorithm can effectively reduce the maximum voltage droop by 6.4%.