FPGA implementation of high speed scalar multiplication for ECC in GF(p)

In this paper, a high speed crypto-processor architecture for computing point multiplication for the elliptic curves defined over the prime field GF(p) is proposed. The proposed architecture uses a multiplier which utilizes parallel one´s counters for accumulation of binary partial product bit. With the increase in speed of multiplication, the speed of ECC point doubling and addition also increases. Also, the architecture takes advantage of an efficient projective coordinates system to convert GF(p) inversion needed in elliptic point operations into several multiplication steps. To increase the processor speed, efficient algorithms are used to compute modular multiplication, addition and subtraction, based on the argument that the speed of the Elliptic Curve Crypto-processor depends on how fast these arithmetic operations can be performed. The proposed architecture for computing 192-bit scalar multiplication for ECC can reach maximum frequency of 191 MHz and occupies 615 slices. It completes one 192-bit scalar multiplication in 676μs.