Finite element analysis of silicon gate all around Nanowire Transistor with different high-k dielectrics

Scaling down of the semiconductor devices from micro to Nano scale has now become the trend for the electronics industry and it is the only hope that can ensure lesser power consumption and also reliability. Ultra thin MOSFET´s, Double Gate MOSFET´s, FINFET and now the latest development is the Nanowire FET. The nanowire FET is a revolutionary device as the gate is all around the channel which provides better gate control and better switching applications. But as the devices are scaled down in size, the oxide layer which lies between the channel and the gate metal is also being reduced in thickness. In this process, when SiO2 is scaled down to nanometer range leakage current is observed in the device which was not prevalent in the micrometer range devices. In this paper, we present the application of high-k dielectrics in use with the Nanowire Field Effect Transistor. The transfer characteristics of the device is studies with three different dielectrics along with the energy band diagrams and trap occupancy in the devices.