Hardware architecture of time domain LTE baseband signal processor

The evolution of wireless technology to its fourth generation has improved exponentially from its predecessor. On the other hand, this improvement requires a higher level of complexity and computation to process the signal. In this paper, we propose an architecture for 4G LTE´s time domain baseband signal processor. To improve the computation time so that it meets the real-time specification, we propose a custom timing synchronization algorithm and FFT implementation. The purpose of this design is to detect the synchronization signal from LTE such as, Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS). The proposed design is written in Verilog HDL and synthesized using Quartus II software, and succesfully implemented in Altera DE4 FPGA board.