Title :
4?4 Bit Multiplier using Adiabatic 2XOR and sleep mode transistor logic
Author :
Sarita Uniyal;Saumya Pandey;Garima Bhargave;Jasdeep Kaur
Author_Institution :
Electronics and Communication Department, IGDTUW, Delhi, India
Abstract :
This paper presents a 4×4 Bit Multiplier using two phase clocked adiabatic static CMOS logic (2PASCL) along with introduction of sleep mode transistor. Modified Adiabatic Multiplier and modified EXOR logic have been implemented on Tanner EDA tool using 180nm CMOS technology. This proposed multiplier attains power savings of 35% to 45% for clock rates changing from 20MHz to 100MHz as compared to existing 2PASCL Multiplier and about 56.25% reduction as that of conventional CMOS circuit at 100 MHz.
Keywords :
"CMOS integrated circuits","CMOS technology","Switches","MOS devices","Yttrium","Simulation","Logic gates"
Conference_Titel :
Signal Processing, Computing and Control (ISPCC), 2015 International Conference on
DOI :
10.1109/ISPCC.2015.7375037