4?4 Bit Multiplier using Adiabatic 2XOR and sleep mode transistor logic

This paper presents a 4×4 Bit Multiplier using two phase clocked adiabatic static CMOS logic (2PASCL) along with introduction of sleep mode transistor. Modified Adiabatic Multiplier and modified EXOR logic have been implemented on Tanner EDA tool using 180nm CMOS technology. This proposed multiplier attains power savings of 35% to 45% for clock rates changing from 20MHz to 100MHz as compared to existing 2PASCL Multiplier and about 56.25% reduction as that of conventional CMOS circuit at 100 MHz.