A low power high speed charge sharing LECTOR comparator

In todays scientific scenario the need for reducing power dissipation for high end devices like Analog to Digital Converters, operational amplifiers is of utmost importance. One of the important contributors to power dissipation is leakage current. In this paper we propose a charge sharing lector comparator which significantly reduces leakage current. The circuit is primarily based on the LECTOR technique with suitable sizing parameters employed to further reduce the power dissipation. This circuit results in the reduction of total average power by 68.83% at a frequency of 100MHz in comparison to charge sharing dynamic latch comparator [1] and delay is minimized to 89.6% .The circuit is implemented on 0.18m and 0.90m CMOS technology.