Comparative analysis of power in Adder using single bit and multi-bit fip-flops, controlled by dynamic hardware control circuit

Any design in VLSI is considered, in terms of area, Speed and Power. The factors interrelated with the above three major factors are Delay, Placement, & Skew. Out of these Delay and Skew are the main timing constraints which have to be considered in VLSI design. Power is a main factor because, an increase in it increases cost in terms of heat sink and hardware required for cooling. In VLSI Flip flops are the majorly clock depended, because their output is dependent on the application of clock pulse, and clock pulse causes the switching of the logic circuits and hence the clock power is of major concern. We get a considerable reduction in power if we reduce the factors which cause power consumption. Multi bit flip flops have been used with this point of view. All the work related to multi bit flip flop has been don at post placement level. In this paper we are focusing multi bit flip-flops at design phase. Considerable work is possible if utilization of flip flops is done properly. We have focused on the application of multi bit flip flop in Adder application and thereby its effect on power, delay and skew. A combination table is built and a dynamic hardware control circuit has been used which will control the utilization of flip flops and only use those flip flops which are needed, depending on the number of bit at the output.