Implementation of AMBA APB bridge with efficient deployment of system resources

The main challenge for a design engineer is not only to design a successful SoC with a well-structured and synthesizable RTL code but also to design it with efficient in energy and optimized in power consumption. The aim of the paper is to implement AMBA APB (advanced microcontroller bus architecture - advanced peripheral bus) Bridge with efficient deployment of system resources. For this, simulation and synthesization of the complex bridge interface is designed which can provide minimum power consumption and low bandwidth between AMBA high speed ASB and low speed APB buses. Clock is a major concern in designing of any digital sequential system. Clock skew is introduced when the difference is generated between the arrival times of clock signal. One of the approaches to minimize clock skew is ripple counter. One can use three bit up or down ripple counter approach. APB Bridge with clock skew minimization technique is implemented in the paper using verilog HDL. For the simulation purpose, ModelSim Version 10.3 has been used. For the synthesization purpose, design utilization summary and power details Xilinx-ISE design suite, version 13.4 has been used. Power report is introduced for developing better understanding of the power utilization in any system. The power report gives the power consumption summary. Hence, the total clocks power consumption is of 0.39 mW, total hierarchy power consumption of 0.57 mW and total on chip logical power consumption of 0.113 W have been extracted from Xilinx XPower analyzer tool when APB bridge is designed under the proposed design approach.