Design and verification of 8b/10b encoder/decoder for USB 3.0 applications

In this paper we have implemented the 8×10 encoder and 10×8 decoder with 3-bit down ripple counter. Ripple counter is one of the techniques for reducing the clock skew problem due to which the power consumption of the circuit can be reduced. This technique is used with encoder and decoder circuit in this paper for reducing the power consumption of the encoder and decoder. The connection between the encoder/decoder and ripple counter circuit is illustrated by RTL schematic shown in Figs. 9 and 11. In this paper, the technology schematic of encoder and decoder with ripple counter is shown in Figs. 10 and 12. At 20 MHz frequency, the clock power of encoder circuit is reduced by 11.11% and the on-chip power of encoder circuit is reduced by 2.70%. For the same frequency the clock power and on-chip power of decoder circuit is reduced by 8.33% and 0% respectively. At 200 MHz frequency, the clock power of encoder circuit is reduced by 10.17% and the on-chip power id reduced by 22.15%. For the same frequency the clock power and on-chip power of decoder circuit is reduced by 7.44% and 4.31% respectively. The 8×10 encoder, 10×8 decoder circuits and 3-bit down ripple counter circuit are design using verilog HDL and are simulated in ModelSim 10.3c. For the RTL schematic, Technology schematic and power report of the implemented circuit we have used Xilinx ISE suite 13.4. The encoder and decoder with ripple counter is verified using FPGA of Kintex 7 family.