Leakage power reduction in MTCMOS based high speed adders

Power and area remain the main constraint in designing of VLSI circuits. Also, adder being one of the main components of processor design is highly researched digital module. In this paper high speed adders are designed using 130nm CMOS process and are being evaluated for their performance at lower technologies. The power dissipation, delay and area are compared for Carry select adder, ripple carry adder and carry look ahead adders. Simulation tools available in Mentor Graphics HEP II package has been used for designing, simulation and for post simulation analysis. It is shown that although the power dissipation and area overhead are high for the carry lookahead adder, the delay is minimum as compared to the other two adders and hence can be used in high speed digital modules. Further it was also shown that by using MTCMOS based design techniques the leakage power can be drastically reduced.