Efficient architectures for parity check matrix generation

New advanced decoding algorithms for error correction systems can improve the frame error rate over commonly used systems. However, they also pose new challenges for their hardware implementations. One part, which consumes a considerable amount of hardware resources, is the storage of the parity check matrix. This problem has not been addressed in literature since it is not yet required by today´s typically applied decoding algorithms. In this paper we investigate sophisticated hardware architectures for storing and generating parity check matrices of BCH, Reed-Solomon and LDPC codes, that exploit the matrix structures. It is shown that these new architectures largely simplify the hardware and require up to five times less area compared to state-of-the-art implementations.