An efficient FPGA implementation of floating point addition

We present an optimized implementation of floating point addition algorithm. The main goal is to reduce design latency as much as possible while maintaining simplicity. We analyze various submodule types in the algorithm and choose the fastest one. Finally, we implement the design in Spartan 6 device, achieving a speed-up of 1.5×, 43.5% less logic levels and occupies 66.5% less slices respectively.