Improved layout implementation of Mini-Mips in terms of power, performance and chip footprint

This paper proposes a customized implementation of Mini-Mips processor; commencing from Register Transfer Level (RTL) down to GDSii Layout level. The implementation is customized for a string matching specific-application that is given problem for second Iranian National Digital Systems Design contest 2015 at Amirkabir University of Technology. We apply various techniques to make reasonable trade-off between area, delay, and power consumption ranging from loop unrolling in algorithm level to low power techniques such as clock gating in circuit level. Moreover, we utilize compiler optimization techniques to reduce the execution time. Our simulations show that execution time is reduced more than 63% on average. In overall, we come up with an optimized design in terms of chip area, power consumption and total execution time.