A low power hybrid MTJ/CMOS (4-2) compressor for fast arithmetic circuits

Compressors are commonly employed in multipliers to reduce the number of partial products and in multi-operand adders to reduce the number of operands. In this paper, a novel magnetic tunnel junction (MTJ) and complementary metal-oxide-semiconductor (CMOS) based architecture is proposed for designing a 4-2 compressor. This architecture reduces the number of elements, connections and circuit complexity, which ultimately results in the reduction of power, delay and chip area. HSPICE Simulations for 32nm technology, through comparisons with previous works in terms of power consumption, delay and power-delay product (PDP), indicate the efficiency of the proposed 4-2 compressor.