Title :
A broadband doubler with harmonic rejection in 90nm CMOS
Author :
Bo-Yu Chen;Yuan-Hung Hsiao;Huei Wang
Author_Institution :
Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan
Abstract :
In this paper, we present a broadband frequency doubler with harmonic rejection using 90nm CMOS process. The balanced frequency doubler adopts cascode topology with class C bias to maximize second order harmonic generation. An elliptic low pass filter is integrated inside the cascode structure to suppress the fourth and higher order harmonic power. The 3-dB bandwidth of this frequency doubler is from 42 to 90 GHz with 8 to 11 dB conversion loss under 5-dBm input drive.
Keywords :
"Power harmonic filters","Harmonic analysis","Broadband communication","Frequency measurement","CMOS integrated circuits","Harmonics suppression","Frequency conversion"
Conference_Titel :
Radio-Frequency Integration Technology (RFIT), 2015 IEEE International Symposium on
DOI :
10.1109/RFIT.2015.7377875
