Directed Symbolic Execution for VLSI Circuits

In this paper we propose a high level test pattern generation scheme for integrated circuits designed at the behavioral level. The scheme is based on the directed symbolic execution that results a symbolic expression for a test path. A test pattern for a circuit under test is derived from actual values of input variables on evaluation of the resulting symbolic expression of a test path and ensures the design correctness. The derived test patterns are further used to measure the percentage of design correctness that directs us to code coverage analysis. We achieve 100% code coverage. Experiments are performed on a number of custom-built and benchmark circuits to validate the proposed test generation. The results from the experiments show as well the performance of the proposed scheme.