Packet Process with Deficit Round Robin ASIC for ATM/Ethernet Bridge

This paper presents a packet process with deficit round robin (DRR) ASIC, which is used not only to give up the first-in first-out (FIFO) mechanism in ATM/Ethernet bridge, but also to integrate with UTOPIA (Universal Test and Operations PHY Interface for ATM) interface between ATM Cell and Ethernet packet. Usually, the packet presents with different weight in the DRR queue. The higher the weight is, the higher the priority is to transmit packet. The proposed DRR ASIC completes the packet process with low delay and low loss. The Alter a DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function, and that the TSMC 0.18μm CMOS technology is used to implement the DRR ASIC after completing the design process, which includes the Synthesis, DFT (Design For Testability), APR (Auto Place and Route) DRC (Design Rule Check) and LVS (Layout Versus Schematic). According to the simulation results, the proposed ASIC performs with the gate count of 31,948 and the power consumption of 8.48 mW.