Configuration circuit design for burn-in test of clb based on structure

As the wide usage of FPGA( Field Programming Gate Array ) in military and aerospace fields, the reliability of FPGA becomes more and more significant. CLB (Configurable Logic Block) is the main logic unit of FPGA, which can realize combinational logic and sequential logic. Dynamic burn-in test is one of the most important tests in reliability assessment of FPGA, which can make potential defects of FPGA exposed. In this paper, the structure and layout of Xilinx Spartan-3 FPGA are analyzed. Combined with the problems of FPGA burn-in, configuration circuit based on structure of CLB is designed. SliceMs are configured into RAM chain mode and shift register mode. SliceLs are configured into 4-input XOR chain mode and 4-input NXOR mode. According to the simulation results, the proposed configuration circuit is input-controllable and output-observable, and the resource utilization is improved.