A 0.25µm SCVL based 4T DRAM design for minimizing leakage current using CMOS technology

With the improved technological development of large ICs, system designers characterized the circuit by reliability, low power dissipation, power consumption, chip density and leakage current. The designers were required to reduce each of these for improved performance, reduced cost and chip size area. CMOS technology increased in level of importance to the point where it now clearly holds the center stage as the dominant VLSI technology. The advanced memories provides considerable capability and extensive application. The main memory is usually of the dynamic random access type. These are highly dense memories with high data storage capability. The major limitation of this memory type is that it losses its data due to the discharge of capacitor and current leakage across the transistors. Thus, they are provided with external refresh circuitry to hold the data increasing the power consumption correspondingly. In this paper we are implementing a low power 4×4 DRAM (Dynamic Random Access Memory) with Self Controllable Voltage Level (SCVL) technique to reduce the leakage current in the design. Simulation is done by using Microwind and DSCH 2.