Design of a low power Adiabatic Logic based Johnson Counter

The paper provides a deep insight to the design of an adiabatic Johnson Counter which consumes low power and delivers high performance. For achieving low power dissipation in circuits the Complementary Pass Transistor Adiabatic Logic (CPAL) is used to design the flip flops. The design of Johnson counter has been simulated and verified. The Tanner EDA tool has been used to simulate all the circuits with 90nm technology. Working within the Mhz frequency band, the proposed design has shown lower power dissipation.