Using Gem5 simulator and DineroIV cache simulator to analyse TLB and Cache statistics with multi threaded Parsec benchmarks

This paper analyses the unicore X86 architecture and records the Translation Look Aside Buffer and Level 2 Cache statistics. These statistics include collecting hits and misses for each memory instruction for both TLB and L2 cache. To bring these statistics together Gem5 simulator and DineroIV cache simulator have been used. After assembling these statistics system´s performance can be inferred. Detailed issues related to this analysis have been discussed in this paper.