Design Successive Approximation Register Analog-to-Digital Converter with Vcm-Based Method for M-PAM Receiver and Computational Intelligence Application

In this paper proposed successive approximation register (SAR) analog-to-digital converter (ADC) implemented for M-PAM receiver and computational intelligence application is presented. By applying Vcm-based switching method that reduces switching power of the DAC, the proposed SAR ADC uses less capacitor in the DAC array. Also, asynchronous control logic is used which an external high frequency doesn´t need clock to drive ADC. This design provide on the automatic gain control (AGC) scheme for pulse amplitude modulation (PAM) with analog-to-digital converters (ADCs).