DocumentCode
3731505
Title
Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories
Author
Masamitsu Tanaka;Kensuke Takata;Takahiro Kawaguchi;Yuki Ando;Nobuyuki Yoshikawa;Ryo Sato;Akira Fujimaki;Kazuyoshi Takagi;Naofumi Takagi
Author_Institution
Nagoya Univ. Nagoya, Nagoya, Japan
fYear
2015
fDate
7/1/2015 12:00:00 AM
Firstpage
1
Lastpage
3
Abstract
We report recent progress in the development of rapid single-flux-quantum (RSFQ) microprocessors integrated with random access memories (RAMs) based on bit-serial processing, called CORE e series. The bit-serial processing is an efficient, unique approach for RSFQ microprocessors that target ultrafast clock frequency with small hardware size. The CORE e series have a richer instruction set and RAMs integrated on the same die, and are capable of running small-scale benchmark programs. We are currently developing three microprocessors in parallel, CORE e2, e3, and e4, for different purposes including prototype demonstration, investigation on efficient use of hardware and energy, and full-function implementation. Here we describe design and implementation of the CORE e microprocessors together with a high-density shift-register-based RAM. The estimated performance of these microprocessors is 333 million instructions per second (MIPS) with 4.6-5.6 mW power.
Keywords
"Microprocessors","Random access memory","Registers","Clocks","Computer architecture","Niobium","Yttrium"
Publisher
ieee
Conference_Titel
Superconductive Electronics Conference (ISEC), 2015 15th International
Type
conf
DOI
10.1109/ISEC.2015.7383449
Filename
7383449
Link To Document