DocumentCode :
3731530
Title :
Numerical Analysis of Thermal Stress in a Voltage Standard Chip
Author :
Hirotake Yamamori;Michitaka Maruyama;Hikari Takahashi;Takahiro Yamada;Yasutaka Amagai;Shogo Kiryu;Hitoshi Sasaki;Nobu-hisa Kaneko;Satoshi Kohjiro
Author_Institution :
NeRI, AIST, Tsukuba, Japan
fYear :
2015
fDate :
7/1/2015 12:00:00 AM
Firstpage :
1
Lastpage :
3
Abstract :
The thermal stress of the voltage standard chip soldered on a copper or sapphire substrate was numerically analyzed by a finite element method. It was confirmed that the thermal stress in the chip soldered on the sapphire substrate is much smaller than that in the chip soldered on the copper substrate. Since the magnitude of the thermal stress applied to the chip depended on the thickness of the substrate, the thickness of the substrate should be properly chosen, e.g., the 0.5-mm thick sapphire minimized the thermal stress for the 0.4-mm thick silicon chip. It was also found that the copper substrate with a few slits did not decrease the risk of the damage due to the thermal stress.
Keywords :
"Substrates","Stress","Copper","Silicon","Thermal stresses","Standards","Thermal analysis"
Publisher :
ieee
Conference_Titel :
Superconductive Electronics Conference (ISEC), 2015 15th International
Type :
conf
DOI :
10.1109/ISEC.2015.7383475
Filename :
7383475
Link To Document :
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