An Improved Simulated Annealing Algorithm and Area Model for the Fixed-Outline Floorplanning with Hard Modules

Fixed-outline floorplanning is a hot issue in physical design, and it is more complicated than outline-free floorplanning since it considers the chip fixed-outline constraints. In this paper, an improved simulated annealing algorithm (ISA) is proposed to solve fixed-outline floorplanning. In case ISA encounters premature convergence, it randomly generates a new floorplan which is independent of the previous one. This simple operation is very efficient to help ISA to get rid of premature convergence. Moreover, a novel area model is constructed to guide ISA to search towards desirable solutions. In addition, B*-tree representation is a simple but efficient method for floorplanning, and thus it is employed here to perturb a solution in each iteration. In the light of experimental results, the proposed method is able to find feasible solutions rapidly, and it outperforms the other methods for most fixed-outline floorplanning problems.