Design optimization of high bandwidth memory (HBM) interposer considering signal integrity

As total system bandwidth increased, memory industry has been imposed to satisfy its requirements. At last, innovative next generation memory named high bandwidth memory (HBM) with extremely fine micro-bump pitch of its bottom die is introduced for terabytes/s bandwidth graphics module. To establish HBM based graphics module, it becomes essential to fabricate silicon interposer due to its capability to process narrow signal width and space. Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. To design HBM interposer successfully, the signal optimization of HBM interposer channels must be preceded thoroughly. In this paper, design optimization of top metal signals of HBM interposer considering routing feasibility is proposed. In order to analyze channel performance to determine optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM interposer are analyzed by comparing eye-opening voltage and timing jitter with 3D electromagnetic (EM) simulation results. Based on this proposed optimization design, not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.