A novel low power keeper technique for pseudo domino logic

Dynamic domino logic circuits are used for high system performance. The dynamic circuits offer superior speed and power dissipation over static CMOS circuits. But these circuits suffer from limitations such as charge leakage, noise and charge sharing. This article provides analysis of the different keeper topologies on pseudo domino logic circuits with reference to power dissipation. The circuit simulations for the analysis of power dissipation have been done on Tanner EDA tool for 45 nm technology. The proposed precharge keeper technique is proffered to economize power dissipation by approximately 45% and transistor count by 25%.