Title :
A low voltage cascode biasing circuit with gain-boosting
Author :
Gowthami Prasanna Banda;Subhajit Sen
Author_Institution :
Department of Electronic System Design, International Institute of Information Technology, Bangalore, India
fDate :
7/1/2015 12:00:00 AM
Abstract :
This paper proposes a new cascode current source circuit that provides high-gain with improved headroom and is suitable for low-voltage amplifiers. The circuit achieves this by modifying a low-voltage cascode gate biasing circuit (“trickle-bias”) such that it amplifies the voltage of the cascode node using a PMOS input folded gain-boost amplifier. The low-voltage current source operates down to 260 mV while providing an improvement of output impedance by a factor of 2.5 as compared to a conventional current source. The proposed cascode current source has been applied to an NMOS input folded-cascode amplifier that gives a gain of 63 dB with a unity-gain frequency of 22.1 MHz at a phase-margin of 64.8° with a total bias current of 30μA operating at a supply voltage of 1.8V.
Keywords :
"Transistors","Impedance","MOS devices","Boosting","Gain","Logic gates","Voltage measurement"
Conference_Titel :
Electronics, Computing and Communication Technologies (CONECCT), 2015 IEEE International Conference on
DOI :
10.1109/CONECCT.2015.7383872