A 1.74mW/GHz 0.11?2.5GHz fast-locking, jitter-reducing, 180? phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers

A 180° phase-shift digital delay-locked loop (DLL) for LPDDR4 memory controllers is composed of a global DLL and a local DLL for each channel. The global DLL uses a time-to-digital converter to achieve fast-locking, and then shuts down to reduce power consumption. The local DLL, locking based on delay codes from the global DLL, uses a digital window phase detector (PD) and tracks the input clock phase to compensate for process, voltage, and temperature variations. Repeatedly controlled window size of the digital window PD in this local DLL reduces the high-frequency jitter compared to the DLL using bang-bang PD. Implemented in 65nm CMOS process, proposed digital DLL dissipates 1.74mW/GHz and occupies 0.074mm². It operates over a frequency range of 0.11-2.5GHz, and locks within 6 cycles at 0.11GHz and within 17 cycles at 2.5GHz. At 2.5GHz, the integrated jitter of the DLL output clock with the digital window PD is 953fs_rms and the long-term jitter of it is 2.64ps_rms and 20.6ps_pp.