A 7T-SRAM with data-write technique by capacitive coupling

A 7T-SRAM, in which cell data is written by capacitive coupling, is proposed. The elimination of current-drive in read/write operation solves current-conflict problems. No degradation of noise margin reduces Vddmin by 0.3V~0.1V. A prototype of 64b 7T-SRAM with 8.74μm2 cell, comparable to 6T-SRAM, using 24nm 3.3V high-voltage CMOS process has been demonstrated for nonvolatile RAMs (NVRAMs) page buffer application. The 7T-SRAM macro has achieved 100% macro yield and low soft error rate (SER) of 400 FIT/Mb at 1.6V Vddmin, which is equal to |Vtp|+|Vtn| for 0.1μA low standby current.