Standing wave based clock distribution technique with application to a 10 ? 11 Gbps transceiver in 28 nm CMOS

Clock distribution becomes a challenge as clock frequency and chip size keep increasing at the same time. Meanwhile, the distributed effects of the clock channel often show up where clock frequency is high and/or it drives large capacitive loading. In these cases, a standing wave-based structure becomes an attractive technique to deliver a low-jitter clock over a long distance with low power consumption. This paper will explore the properties of a standing wave resonator and its applications in clock distribution. The introduced technique was demonstrated with a design that delivers 5.5GHz quadrature clock to ten lanes of TX/RX and only consumes 12mW. The ten lanes, each running at 11Gbps, showed consistent and excellent jitter performance in measurement, verifying the proposed technique.