A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation

This paper presents a 6-bit 3.4 GS/s flash ADC in 65 nm CMOS. The proposed 4× time-domain interpolation technique allows the reduction of the number of comparators from the conventional 63 to 16 in a 6-bit flash ADC. Without extra clocking and calibration in the interpolated stage, the proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches. Offset calibration is only applied to the comparators and implemented on-chip. Measurement results show that the prototype can achieve 3.4 GS/s with a total power consumption of 12.6 mW at 1 V supply. Besides, it exhibits a 34.2 dB SNDR at Nyquist, which yields a Walden FoM of 89 fJ/conversion-step.