A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers

This paper presents a 9-bit 1.8-GS/s pipelined ADC. It employs open-loop residue amplifiers with a linearization technique, two time-interleaved CDACs with stage gain calibration, and a double-sampling architecture. This open-loop structure achieves high speed, low power and moderate resolution without any digital nonlinearity calibrations. The fabricated ADC in 65-nm CMOS technology achieves an SNDR of 51 dB and a FoM of 83 fJ/conversion-step while the sampling rate is 1.8 GS/s.