A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW

Fully automated Verilog-to-layout synthesis of ADCs using custom analog cells is presented. Previous work in synthesized ADC design used only the standard digital library, and consequently the achieved resolution has been extremely limited. This work adds rudimentary analog components alongside the standard digital library, then uses Verilog code to describe analog functions and synthesize it into layout. The same Verilog code is used to create a MASH ADC in both 65nm and 130nm CMOS, demonstrating 56dB SNDR with ≥2MHz bandwidth. The ADCs occupy 0.014mm² and 0.046mm², respectively. Using the same Verilog code demonstrates the rapid portability and scalability of this design procedure.