A complete Verilog-A Gate-All-Around junctionless MOSFET model

In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Around (GAA) long-channel junctionless MOSFET model in Verilog-A code, which will be further used in commercial circuit simulators. The model in Verilog-A is integrated in the SmartSpice circuit simulator and tested in a CMOS inverter. Both p-channel and n-channel device models are validated. Also, the results are compared with data from 3D numerical simulations, showing a very good agreement in all transistors´ operation regimes.