Multi-level probabilistic timing error reliability analysis using a circuit dependent fault map generation

This paper proposes a methodology for timing error analysis of RTL circuit descriptions. The evaluation has three components: (i) statistical static timing analysis (SSTA) for standard cell components (ii) estimation based on probability density function (PDF) propagation for characterization of combinational blocks, and (iii) simulated fault injection (SFI) performed at RTL. Reliability characterization of basic components is derived using SSTA; PDF propagation is used to accurately capture the probabilistic error profile of each primary output (PO) of combinational blocks; RTL saboteur based SFI is employed in order to assess the reliability of the whole circuit. The proposed methodology is applied for the fault tolerance analysis of a flooded Min-Sum (MS) LDPC decoder.