DocumentCode :
3734603
Title :
Improving robustness of dynamic logic based pipelines
Author :
H?ctor J. Quintero;Mar?a J. Avedillo;Juan N??ez
Author_Institution :
Instituto de Microelectr?nica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Av. Am?rico Vespucio s/n 41092, (Spain)
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the non-inverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its non-inverting feature.
Keywords :
"Logic gates","Delays","Pipelines","Discharges (electric)","Robustness","Pipeline processing","Clocks"
Publisher :
ieee
Conference_Titel :
Design of Circuits and Integrated Systems (DCIS), 2015 Conference on
Type :
conf
DOI :
10.1109/DCIS.2015.7388597
Filename :
7388597
Link To Document :
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