DocumentCode
3734701
Title
Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS
Author
Odysseas Zografos;Bart Sor?e;Adrien Vaysset;Stefan Cosemans;Luca Amar?;Pierre-Emmanuel Gaillardon;Giovanni De Micheli;Rudy Lauwereins;Safak Sayan;Praveen Raghavan;Iuliana P. Radu;Aaron Thean
Author_Institution
imec, Leuven, Belgium
fYear
2015
fDate
7/1/2015 12:00:00 AM
Firstpage
686
Lastpage
689
Abstract
In this paper, we present a design and benchmarking methodology of Spin Wave Device (SWD) circuits based on micromagnetic modeling. SWD technology is compared against a 10nm FinFET CMOS technology, considering the key metrics of area, delay and power. We show that SWD circuits outperform the 10nm CMOS FinFET equivalents by a large margin. The area-delay-power product (ADPP) of SWD is smaller than CMOS for all benchmarks from 2.5× to 800×. On average, the area of SWD circuits is 3.5× smaller and the power consumption is two orders of magnitude lower compared to the 10nm CMOS reference circuits.
Keywords
"Integrated circuit modeling","Magnetoelectric effects","Perpendicular magnetic anisotropy","Switches","CMOS integrated circuits","Semiconductor device modeling"
Publisher
ieee
Conference_Titel
Nanotechnology (IEEE-NANO) , 2015 IEEE 15th International Conference on
Type
conf
DOI
10.1109/NANO.2015.7388699
Filename
7388699
Link To Document