• DocumentCode
    3734862
  • Title

    The nanodamascene process: A versatile fabrication technique for nanoelectronic applications

  • Author

    D. Drouin;G. Droulers;M. Labalette;B. Lee Sang;P. Harvey-Collard;J.-P. Richard;M. Pioro-Ladriere;S. Ecoffey;A. Souifi;S. Monfray

  • Author_Institution
    LN2 - Laboratoire Nanotechnologies Nanosystemes, (LN2) - CNRS UMI-3463, Canada
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    1262
  • Lastpage
    1266
  • Abstract
    In this paper we present a versatile nanodamascene fabrication process for the realization of low power nanoelectronic devices. This process has been exploited for the fabrication of metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar nanometric resistive memories. Due to its low thermal budget, and materials, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.
  • Keywords
    "Silicon","CMOS integrated circuits","Three-dimensional displays","Fabrication","Junctions","Metals","Nanoscale devices"
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology (IEEE-NANO) , 2015 IEEE 15th International Conference on
  • Type

    conf

  • DOI
    10.1109/NANO.2015.7388860
  • Filename
    7388860
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3734862