Small area VLSI architecture for deblocking filter of HEVC

In this paper, a small area hardware architecture for deblocking filter of HEVC is proposed. To achieve high throughput and small area, an efficient processing order based on a CTU-based pipeline is proposed. The proposed architecture is synthesized in ALTERA Cyclone V 28nm process FPGA with 28.7K gate counts. The simulation result shows that the proposed architecture achieves an area reduction of 32% compared with the architecture which uses similar cross unit. About throughput, the proposed architecture uses 24 clock cycles for a 16×16 unit and achieves real-time processing for quad full high definition (QFHD) resolution videos with 60fps.