Programmable mask design for Phase Controlled Thyristors with automated short positioning

Procedural layout generation is common practice in digital, analog or RF circuit layout design. Designers generate mask designs by specifying only the key parameters of devices, digital or analog blocks and have algorithms construct the complete layout. But automated layout design is limited to Manhattan structures (orthogonal shapes) or to devices with 45° angles (typically octagonal inductors). This work introduces for the first time procedural layout generation to wafer-size power semiconductor devices such as Phase Controlled Thyristors (PCTs), characterized by arbitrary angles and shapes, including curved geometries. The proposed technique offers many advantages such as saving of time, automatic enforcement of design rules and best practices, and ease of modification of an existing design. In particular, this work focuses mainly on the key advantage of this approach: device performance and reliability improvement through automated placement of the PCT shorts.