Clock speed optimization of runtime reconfigurable systems by signal latency measurement

Partial runtime reconfiguration is a feature of modern Field Programmable Gate Arrays (FPGAs). It allows the reconfiguration of some parts of the FPGA, while other parts are still running and doing computations. The design flow to create a partially run-time reconfigurable system includes the partitioning of a FPGA into multiple collaborating Reconfigurable Modules (RMs), as part of the floor-planning design stage, and the development of an interconnection network. The latency of the chosen interconnection network determines the maximum clock speed the components inside the RMs can run at. The customary way of choosing design constraints to achieve the highest possible speed can lead to very long placement and routing times or even to an un-routable design. Eventually, the the Time To Market (TTM) of a product can be inreased. This paper proposes measuring the latencies of the interconnection network after a relaxed configuration phase. This is achieved by configuring two different kinds of components into the RMs and measure the round trip time of the network between them. Thus, the best placement of reconfigurable components, as well as the maximum clock rate of a given configuration can be calculated, and set without the need to rebuild the system. This enables the developer to place components into the RMs according to their clock speed requirements, without the need to reconfigure or rebuild the full system. This paper also presents some example measurements and an example placement of a small microcontroller.