Verification and validation based on the generation of testing sequences from timing diagram specifications in industrial automation

We present Timing Diagram Testing for Verification & Validation (T4V, which is red as "tav") for Industrial Automation Systems. T4V is our approach to address the problem of generating test sequence to verify & validate (V&V) industrial automation systems software. T4V aims to solve this problem by generating test sequences from the timing diagrams of software specifications. Then, run them in Real-Time (RT) onto the PLC, check part of their conformance on-the-run, save the test outlines, and automatically analyze the outlines through an algorithmic verification. We currently implemented T4V for IEC61131-3 platforms (e.g. Beckhoff TwinCAT3) and Rockwell Automation PLCs, but we are integrating it only in our testing and V&V platform for Beckhoff PLCs. We believe that T4V may simplify and/or face the challenges of V&V in order to enable a more efficient and effective testing. Moreover, we believe that it could help PLC providers to understand the needs of an environment with testing and V&V features integrated.