DocumentCode
3738038
Title
An Implementation of Trax player using programmable SoC
Author
Akira Kojima
Author_Institution
Department of Computer and Network Engineering, Hiroshima City University, Japan
fYear
2015
Firstpage
268
Lastpage
271
Abstract
In this paper, we describe our implementation of Trax player on Xilinx Zynq programmable SoC for ICFPT2015 design competition. Our design uses Alpha-Beta pruning algorithm to find the best next move from the game tree. As thinking time for one turn is limited to one second by the competition rule, we also use iterative deepening algorithm and timer hardware. Evaluation function which is used for the leaf nodes of the game tree detects simple attacks, simple corners, and victory line candidates and calculates the value of the existing tiles. Hotspot software code detected by profiling is translated into HDL code using a high level synthesis tool.
Keywords
"Games","Hardware","Algorithm design and analysis","Field programmable gate arrays","Software","High level synthesis","Joining processes"
Publisher
ieee
Conference_Titel
Field Programmable Technology (FPT), 2015 International Conference on
Type
conf
DOI
10.1109/FPT.2015.7393121
Filename
7393121
Link To Document