Floating point CORDIC-based architecture for powering computation

This work presents an architecture for powering computation in floating point arithmetic that is based on an expanded hyperbolic CORDIC algorithm, where the user can select the 2-D domain of convergence that suits their application. The fully parameterized hardware implementation allows us to explore trade-offs among design parameters (numerical format, number of iterations), resource usage, accuracy, and execution time. We carry out an exhaustive design space exploration and generate Pareto-optimal realizations in the resource-accuracy space. Our approach allows us to select optimal hardware realizations that meet or exceed accuracy requirements.