UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs

FPGA vendors now include hardened IPs to form a system-on-chip (SoC) making it easier to build embedded systems. However programming and integrating hardware accelerators (devices) into these systems present a challenge. The OpenCL standard has become accepted as a good programming model for managing devices, or hardware accelerators in the context of embedded systems on FPGAs, due to its rich set of constructs. OpenCL has also caught the attention of FPGA vendors for use in high-level systhesis (HLS). While commercial OpenCL frameworks are now emerging, there is a need for an open-source OpenCL framework that facilitates the exploration of the overall system architecture and software, as well as the implementation and architectures of the task-level parallel devices. This would enable exploration of concepts that can improve current architectures as well as allow the study of features that are not within the current standard. This paper presents UT-OCL, an OpenCL framework for embedded systems using FPGAs. The framework is composed of a hardware system and its necessary software counterparts, which together form an embedded Linux system augmented to run OpenCL applications within a single FPGA. This paper describes the challenges with implementing an OpenCL framework for embedded systems on FPGAs, and presents an OpenCL implementation that is compliant with OpenCL 2.0. This framework is intended for use as a platform to explore architectures for hosting OpenCL applications, implemetations of OpenCL features and to study potential new features for OpenCL. Although the current trend is to use OpenCL in high-level synthesis targeting FPGAs, it is not the focus of this paper.